The present invention relates in general to electronic circuits, and is particularly directed to new and improved current mirror circuit architecture for minimizing transistor base current errors or offsets in a low voltage application such as, but not limited to the, coupling of a subscriber line interface circuit to a low voltage codec.
Systems employed by telecommunication service providers contain what are known as subscriber line interface circuits or xe2x80x98SLICxe2x80x99s, to interface communication signals with tip and ring leads of a wireline pair that serves a relatively remote piece of subscriber communication equipment. In order that they may be interfaced with a variety of telecommunication circuits, including those providing codec functionality, present day SLICs must conform with a very demanding set of performance requirements, including accuracy, linearity, insensitivity to common mode signals, low noise, low power consumption, filtering, and ease of impedance matching programmability.
Indeed, using differential voltage-based implementations, designers of integrated circuits employed for digital communications, such as codecs and the like, have been able to lower the voltage supply rail requirements for their devices (e.g., from a power supply voltage of five volts down to three volts). As a result, the communication service provider is presented with the problem that such low voltage restrictions may not provide sufficient voltage headroom to accommodate a low impedance-interface with existing SLICs (which may be designed to operate at a VCC supply rail of five volts).
This limited voltage headroom problem may be illustrated by considering the design and operation of a conventional current mirror architecture, such as that shown in FIG. 1, which is of the type that may be employed in a subscriber line interface circuit, being designed to operate with a customary VCC supply rail of five volts. In this conventional current mirror design, an input NPN transistor 10 has its base 11 coupled to a voltage reference VREF, and its emitter 12 coupled to receive an emitter current I12 or input current Iin, from a device, such as a codec.
The collector 13 of the input NPN transistor 10 is coupled in common to the collector 23 of a first current mirror input PNP transistor 20, and to the base 31 of a base current compensator PNP transistor 30, the collector 33 of which is coupled to a voltage reference terminal, such as ground (GND). The emitter 32 of the base current compensator PNP transistor 30 is coupled in common to the base 21 of the current mirror input transistor 20 and to the base 41 of a PNP current mirror output transistor 40. The emitters 22 and 42 of current mirror transistors 20 and 40, respectively, are coupled through resistors 24 and 44 to a (VCC) voltage supply rail 16, while the collector 43 of the current mirror output transistor 40 is coupled to an output terminal 45, from which an output current Iout is derived.
Although working reasonably well when operating at a designed power supply rail voltage VCC of five volts, the current mirror of FIG. 1 lacks sufficient overhead for proper circuit operation with a reduced voltage circuit, such as a differential voltage-based codec operating at a much smaller VCC rail value (e.g., on the order of only three volts and a reference voltage VREF of only half that). In addition, even though the mirrored output Iout at the output node 45 is first order compensated for PNP base current errors, it is not compensated for the NPN base current error in the input transistor 10.
More particularly, the mirrored output current Iout at the current mirror""s output terminal 45 corresponds to the collector current I43 flowing out of the collector 43 of the current mirror output transistor 40 which, for equal geometry current mirror input and output transistors and equal value resistors 24 and 44, may be defined as:
Iout=I43=xcex1NPN10I12xe2x88x922I12/xcex2PNP2,
or
xe2x80x83Iout=I12(xcex1NPN10xe2x88x922/xcex2PNP2).
Therefore, for all practical purposes the value of the mirrored output current Iout may be approximated as:
Iout=Iin(1xe2x88x921/xcex2NPN).xe2x80x83xe2x80x83(1)
From equation (1), it can be seen that the mirrored output current Iout at the collector 43 of the current mirror output transistor 40 not only includes the desired input current Iin, but contains an undesired base current error component Iin/xcex2NPN associated with the NPN input transistor 10. Due to the extremely tight voltage tolerances associated with the use of the substantially lower VCC supply rail voltage and reference voltage VREF, there is no available headroom in the collector-emitter current flow path through transistors 10-20 and the VCC supply rail for insertion of an NPN base current error compensating transistor.
In an alternative architecture, the input transistor 10 is removed, so that the input is applied directly to the collector 23 of the current mirror input transistor 20. However, this does not resolve the base current error problem, since the overhead voltage at the input (the collector 23 of the current mirror input transistor 20) is still two base-emitter diode voltage drops (Vbe20+Vbe30) below VCC.
In this case the mirrored output current may be defined as:
Iout=Iin(1xe2x88x921/xcex2p2).xe2x80x83xe2x80x83(2)
In accordance with the present invention, the above-described base current error problem is successfully addressed by a multiple transistor polarity (PNP and NPN) base current error reduction and auxiliary turn-on circuit architecture, that provides an overhead voltage that enjoys a base-emitter diode drop improvement over the overhead voltage of a conventional circuit. As in the conventional current mirror architecture of FIG. 1, the improved base current error minimizing current mirror circuit architecture of present invention couples the base of the current mirror input transistor to the emitter of a base current compensator transistor.
However, rather than having its base connected directly to the collector of the current mirror input transistor, the base current compensator transistor has its base coupled to the emitter of an opposite polarity base current error-reduction transistor. This base current error-reduction transistor has its collector coupled to the VCC supply rail, and its base coupled to the collector of the current mirror input transistor, to which the current mirror""s input terminal is coupled.
The emitter of the base current error-reduction transistor is further coupled to the collector of the base current compensator transistor through an auxiliary biasing and turn-on circuit including a pull down transistor pair. In addition, a diode is coupled between the base current compensator transistor and the input port, and serves to ensure that the circuit turns on in the presence of a slowly ramping power supply.
Due to the presence of the base current error-reduction transistor in the circuit path from the power supply rail to the input port, the overhead voltage is improved by a base-emitter diode drop when compared to the overhead voltage of the conventional circuit. In addition, the presence of the auxiliary biasing circuit allows for further reduction of the base current error, as will be described.